1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a method for forming a via in a semiconductor manufacturing process, capable of vertically maintaining a profile of a via contact hole by forming a protective film at a side surface of an SOG film, exposed by a via contact hole etching process, by Ar plasma treatment in order to prevent an undercut profile of the via contact hole from being formed in case the via contact hole is formed by using an SOG (spin-on-glass) film as an insulated film.
2. Discussion of the Background
In a conventional semiconductor manufacturing process, a via is formed by reactive ion etching (RIE), plasma etching, etc., Recently a high density plasma etching method has been used in a process for forming the via.
A conventional method for forming a via using the plasma etching method will be described with reference to the accompanying drawings.
FIGS. 1A through 1E are vertical cross-sectional diagrams sequentially illustrating a conventional method for forming a via.
In FIG. 1A, a conductive layer pattern 2 is formed on a base layer 1 on a semiconductor substrate (not shown). A plurality of semiconductor devices (not shown) are formed in the base layer 1. The conductive layer pattern 2 is formed by depositing a conductive layer (not shown) on the base layer 1 and selectively etching the conductive layer using an etching mask.
In FIG. 1B, a first insulating layer 3, a second insulating layer 4, and a third insulating layer 5 are sequentially formed on the base layer 1 having the conductive layer pattern 2 formed thereon. The first insulating film 3 and the third insulating film 5 are formed of SiO.sub.2 or Si.sub.3 N.sub.4, or a combination thereof by CVD, and the second insulating film 4 is formed of a SOG film.
In FIGS. 1C and 1D, a photoresist pattern 6 is formed on the third insulating film 5. Using the photoresist pattern 6 as a mask, a plasma etching process is used to etch the first, second, and third insulating layers 3, 4, 5 to expose an upper surface of the conductive layer pattern 2, thus forming a via 7. Here, the photoresist pattern 6 is formed by forming a photoresist layer (not shown) on the third insulating layer 5 and exposing and developing the photoresist layer . In the plasma etching process, the semiconductor substrate (not shown) having the photoresist pattern 6 formed thereon is placed in a chamber of a plasma etching apparatus (not shown). An etching gas is supplied to the chamber. A plasma generated by applying radio frequency power to the etching gas is vertically flowed to the semiconductor substrate. Here, the photoresist pattern 6 is used as a mask for forming the via 7, and fluorocarbon, hydrofluorocarbon, inert gas, or oxygen, or combination thereof are used as the etching gas.
In FIG. 1E, the photoresist pattern 6 and remains in the via 7 are removed by an O.sub.2 plasma treatment, thus completing the conventional method for forming a via. Here, when removing the photoresist pattern 6 and the remains in the via 7, a side surface of the second insulating film 4, the SOG film, which corresponds to a profile of the via 7, is inwardly bowed.
In the above-described conventional method for forming the via, an undercut profile of the via contact hole is formed because the side surface of the SOG film is inwardly bowed by reaction of oxygenic elements of O.sub.2 plasma, (applied to removing the photoresist pattern and the remains in the via) and carbonaceous elements of the SOG film.
In addition, when depositing an interconnection metal layer, a profile of the deposited interconnection metal layer consequently has a negative tilt. Therefore, an open circuit state where no connection is made between interconnection metal layers can occur.
Also, in a borderless via contact process, since a marginal portion of a lower metal interconnection layer is partially exposed, the undercut profile of the via contact hole is more seriously formed in the conventional etching process.